package yycore

import chisel3._
import chisel3.util.experimental.BoringUtils
import common.Constants._
import bus._
import top._
import utils.PipelineConnect

class MyCore extends Module {
  val io = IO(new Bundle() {
    val flush = Output(Vec(2, Bool()))
    val dmem = new CoreLinkIO(XLEN)
    val imem = new CoreLinkIO(XLEN)
    val dmmio = new CoreLinkIO(XLEN)
  })
  io := DontCare

  // create components that is if, decode, execute, memory, writeback
  val frontend = Module(new Frontend)
  val backend = Module(new Backend)

  val addrSpace = List(
    (0x80000000L, 0x80000000L),
    (Settings.getLong("MMIOBase"), Settings.getLong("MMIOSize")), // external devices
  )

  frontend.io.out <> backend.io.in
  frontend.io.redirect <> backend.io.redirect
  frontend.io.flush := backend.io.flush(0)
  io.flush.zipWithIndex.map { case (f, i) =>
    f := backend.io.flush(i)
  }

  io.imem  <> frontend.io.imem
  io.dmem <> backend.io.dmem
  io.dmmio <> backend.io.mmio

}

